The present invention generally relates to semiconductor processing, and more particularly to a method of fabricating isolation regions, such as shallow trench isolation (STI), using an ultra-thin separation by ion implantation of oxygen (SIMOX) process.
One of the first widely practiced isolation schemes for isolating devices was called local oxidation of silicon (LOCOS). In the LOCOS process, a pad oxide and a pad nitride are patterned on a Si surface. The exposed regions of Si are oxidized while the patterned regions are prevented from oxidation. The problem with the LOCOS process is that lateral oxidation occurs causing a “bird's beak” which limits the usable active area size.
In the semiconductor industry, it is currently well known to isolate one or more device regions present on a semiconductor structure using isolation regions such as shallow trench isolation (STI) regions. State-of-the-art STI processing includes many steps that are time consuming and which add extra cost to the overall fabrication of a semiconductor device.
A standard STI process is shown, for example, in FIGS. 1A-1C. Specifically, prior art FIG. 1A illustrates an initial processing step in which a pad stack comprising an oxide 12 and a nitride 14 is formed atop a surface of a semiconductor substrate 10. An optional hard mask (not shown) may also be formed atop the nitride layer 14 of the pad stack.
Next, lithography is employed in providing a trench pattern to the structure. Specifically, the trench pattern is formed by first applying a photoresist on the upper surface of the pad stack. The photoresist is then exposed to a pattern of radiation and thereafter the pattern in the photoresist is developed using a resist developer. An etching step is used to transfer the pattern from the photoresist into the nitride layer 14. After the initial pattern transfer, the photoresist is removed utilizing a stripping process and then etching continues through the oxide layer 12 stopping atop an upper surface of semiconductor substrate 10 so as to provide a structure having an opening 16 in the oxide layer 12 as shown, for example, in FIG. 1B.
After providing the structure shown in FIG. 1B, a trench is formed in the semiconductor substrate 10 via etching through the opening 16. A trench liner 20 is typically formed via oxidation on the bare sidewalls of the trench including the sidewalls of the oxide layer 12. The trench is then filled with a trench dielectric material 22 such as SiO2, tetraethylorthosilicate (TEOS) or a high-density plasma oxide and thereafter the structure is planarized to the upper surface of the nitride layer 14. A deglazing process may follow the trench fill step. After deglazing, the nitride layer 14 is removed providing a structure having an STI region 24 formed in the surface of semiconductor substrate 10. The structure including STI region 24, which includes liner 20 and dielectric fill 22, is shown, for example, in FIG. 1C. The oxide layer 12 is then removed by chemical mechanical polishing (CMP).
In addition to being time consuming and costly, STI regions produced from the prior art process mentioned above may contain divots at the STI/substrate corners. The presence of divots at the STI/substrate corner is undesirable since divots create unwanted features such as polysilicon rails and an early “turn-on” characteristic in the device.
In view of the drawbacks mentioned above with the prior art, process of fabricating STI regions, there is a need for providing a simplified method of forming isolation regions such as STIs, which provides equivalent or improved isolation performance, yet at a distinct cost advantage as compared with the prior art process.